SPC58NH92C5 - 用于汽车一般用途应用的32位Power Architecture MCU - Chorus系列, SPC58NH92C5RMI0X, SPC58NH92C5HMI0X, S

所有功能

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• AEC-Q100 qualified
• High performance e200z4 triple core:
  • 32-bit Power Architecture technology CPU
  • Core frequency as high as 200 MHz
  • Variable Length Encoding (VLE)
  • Floating Point, End-to-End Error Correction
• 10496 KB (10240 KB code Flash + 256 KB data Flash) on-chip Flash memory:
  • Supports read during program and erase operations, and multiple blocks allowing EEPROM emulation
  • Supports read while read between the two code Flash partitions
  • Hardware support for Flash context switching (for FOTA with multi software versions)
• 1088 KB on-chip general-purpose SRAM (in addition to 192 KB core local data RAM):
  • 64 KB in CPU_0, 64 KB in CPU_1 and 64 KB in CPU_2
• 224 KB HSM dedICated Flash memory (192 KB code + 32 KB data)
• Multi-channel direct memory access controller (eDMA):
  • One eDMA with 64 channels
  • One eDMA with 16 channels
• One interrupt controller (INTC)
• Comprehensive new generation ASIL-D safety concept:
  • ASIL-D of ISO 26262
  • One CPU channel in lockstep
  • Logic BIST
  • FCCU for collection and reaction to failure notifications
  • Memory BIST
  • Cyclic redundancy check (CRC) unit
  • Memory Error Management Unit (MEMU) for collection and reporting of error events in memories
• Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC
• Body cross triggering unit (BCTU):
  • Triggers ADC conversions from any eMIOS channel
  • Triggers ADC conversions from up to 2 dedicated PIT_RTIs

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• Enhanced modular IO subsystem (eMIOS):
  • up to 96 timed IO channels with 16-bit counter resolution
• Enhanced analog-to-digital converter system with:
  • 4 independent fast 12-bit SAR analog converters
  • One supervisor 12-bit SAR analog converter
  • One standby 10-bit SAR analog converter
  • 100 ADC channels
• Communication interfaces:
  • 24 LINFlexD modules
  • 10 deserial serial peripheral interface (DSPI) modules
  • 1 deserial serial peripheral interface (DSPI_LP) module available in low power mode
  • 16 MCAN interfaces with advanced shared memory scheme and ISO CAN-FD support
  • Dual-channel FlexRay controller
  • One SD/SDIO/eMMC module
  • One OctalSPI module with double Chip Select
  • Two independent Ethernet controllers, one 10/100Mbps and the other one 10/100Mbps or 1Gbps, compliant IEEE 802.3-2008 and OPEN RGMII EPL v2.3
  • Four I2C modules
  • Two PSI5 modules
• Low power capabilities:
  • Versatile low power modes
  • Ultra low power standby with RTC
  • Smart Wake-up Unit for contact monitoring
  • Fast wakeup schemes
• Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell
• Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some support for 2010 standard
• Boot assist Flash (BAF) supports factory programming using a serial bootload through the asynchronous CAN or LIN/UART
• Low power supply options:
  • Single internal linear regulator with external ballast
  • External low voltage supply (1.2V)
• Temperature range:
  • -40 °C to 105 °C
  • -40 °C to 125 °C

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